The research investment cycle

Semiconductor investment is often described through factories and manufacturing tools. The June 2025 SIA report examines a different part of the cycle: shared research infrastructure intended to make new technologies usable in manufacturing. Its focus includes packaging, prototyping, digital models and measurement. This is a dated account of program design and funding, not proof that every planned facility is now operating. The distinction matters because an allocation can support an innovation agenda without yet producing a qualified process or a commercial product.

Read allocations as allocations

The funding chart on page 6 lists US$6,355 million for the National Semiconductor Technology Center (NSTC), US$3,000 million for the National Advanced Packaging Manufacturing Program (NAPMP), US$285 million for SMART USA and US$252 million for metrology. NSTC and NAPMP must not be swapped: their chart legend assigns the larger allocation to NSTC. These are the program allocations described in the June 2025 report, not annual R&D expenditure by listed companies and not cash already spent. (SIA, June 2025, p. 6, CHIPS R&D Program Funding chart.)

Four complementary research functions

NSTC is described as supporting prototyping and collaboration across the technology stack. NAPMP focuses on advanced packaging: how dies are connected and integrated into a working system. SMART USA concerns digital twins, meaning digital models of physical systems and processes. Metrology is the measurement work needed to characterize and verify those processes. These functions are complementary, not four interchangeable sources of funding. (SIA, pp. 7–13.)

Access is different from a finished result

The report describes programs that create places to collaborate and test ideas. Access to shared infrastructure can be analytically different from owning a commercial production line. The key milestones are whether facilities become available, whether research agendas match practical manufacturing problems and whether results can be transferred into repeatable production. This source describes the intended connections; it does not establish the future revenue of a participating company or quantify a return on public funding. (SIA, pp. 3 and 10–14.)

Keep public programs and company R&D separate

Program allocations cover a different scope and period from a company’s annual research expense. Combining them in one spending ranking would create a misleading comparison. Likewise, a planned award, a signed agreement and a completed research milestone are not the same event. The defensible use of the chart is to show the relative scale of the named allocations in the source, not to claim that the US innovation cycle has already delivered a particular commercial outcome.

The evidence needed next

An updated assessment would require dated program records on awards, facility access and research milestones. Because the underlying status is from June 2025, this article keeps all program-specific statements tied to that report. It deliberately leaves out the report’s comparison with a Chinese research-spending figure: that number covers multiple technologies and is supported there by a secondary news source, so it is not a like-for-like primary-source comparison of semiconductor R&D.