The Race to 1 nm — and the Chip Economy Beyond It

A smaller number can signal a major engineering achievement. It cannot tell you, on its own, which chip is more profitable, which factory will earn the best return, or which component will constrain the next wave of AI infrastructure.

Understanding the move towards 2 nm, 1.4 nm and eventually 1 nm requires three separate maps: the technology roadmap, the products using each process, and the market that pays for them. Those maps overlap, but they do not move in lockstep.

The useful question for investors is therefore broader than who reaches the smallest node first: where does a new process create enough economic value to justify moving to it?

What a node actually tells you

A process node is a manufacturing platform: its transistor architecture, interconnects, design rules and fabrication steps. Intel explains that modern node names represent generations of density or performance improvement more than literal physical dimensions. A “2 nm chip” does not consist of transistors whose every dimension measures two nanometres.

An ångström is one-tenth of a nanometre, so 18 Å converts to 1.8 nm as a unit of length. But Intel 18A, TSMC N2 and Samsung SF2 are distinct technologies. Their names do not establish an apples-to-apples ranking. Customers also evaluate performance, power, density, manufacturing yield and cost.

2 nm is commercial; 1 nm remains a future frontier

TSMC says N2 entered volume production in 2025. The supplied annual-report reference schedules N2P and A16 for the second half of 2026; that document could not be accessed in this review, so the precise schedule remains subject to verification. These milestones need careful interpretation: starting production, achieving attractive yields and generating a large revenue contribution are different stages.

TSMC’s published A14 targets illustrate what the next step is meant to deliver: up to 15% higher speed at the same power, or up to 30% lower power at the same speed, plus more than 20% higher logic density versus N2. The alternatives matter: these are not simultaneous gains to add together, and they are process targets rather than guaranteed improvements in a finished device.

The subsequent roadmap already has branches. TSMC’s A13 is a direct shrink of A14 with 6% area savings, while A12 brings backside power delivery to the platform. Both are scheduled for 2029. That is a more informative picture than a single descending sequence of node numbers.

For 1 nm, the responsible framing is a technology frontier. Imec’s research addresses the transistor, interconnect and lithography changes needed to keep scaling. A research demonstration or roadmap label is not proof of economical high-volume manufacturing. This article therefore assigns neither a firm commercial launch date nor a current market share to 1 nm.

Which chips actually use which nodes?

Specific products are more useful than blanket rules such as “AI uses 2 nm” or “cars use old chips.” The examples below are selected, manufacturer-documented implementations, not an exhaustive catalogue or a ranking of the newest products in each category.

AMD’s Ryzen 9 7950X makes the multi-node point concrete: its CPU cores use TSMC 5 nm, while its I/O die uses 6 nm. Assigning the entire package one node loses useful information about its design and manufacturing economics.

Blackwell is a useful counterexample to the assumption that a commercially important AI accelerator must use the smallest available node. NVIDIA specifies a custom TSMC 4NP process and two connected GPU dies—individual pieces of silicon within the product. Product architecture and integration belong in the analysis alongside manufacturing technology.

Memory has its own naming system

DRAM labels such as 1α, 1β and 1γ should not be placed on a logic-node chart as 1 nm. Micron describes 1α as a generation within the 10 nm class. High-bandwidth memory (HBM) is a stacked-memory technology and packaging arrangement, not one universal process node.

A further complication is the distinction between an HBM stack’s logic base and its memory dies. The supplied manuscript names TSMC N12 and N3 base dies for HBM4, but that specific mapping lacks a traceable primary-source reference and remains unverified in this draft.

The revenue mix tells a different story from the headlines

In Q2 2026, TSMC reported that 2 nm generated 3% of wafer revenue, compared with 30% for 3 nm, 33% for 5 nm and 11% for 7 nm. Together, 7 nm and smaller represented 77%. The remaining 23% came from the older categories shown below.

The interpretation is straightforward: a node can lead technologically before it dominates commercially. Existing designs and subsequent product generations can keep established processes economically relevant.

There is also a measurement trap. Expensive wafers can carry more revenue weight than their production volume suggests. TSMC’s mix cannot establish what percentage of all the world’s chips uses 2 nm. It is one foundry’s revenue disclosure. At the research cut-off, its Q3 earnings conference was scheduled for 15 October; this chart uses the published Q2 node breakdown.

The wider market: a powerful, uneven expansion

SIA reports global semiconductor sales of $795.6 billion in 2025. Its 5 October 2026 release puts August sales at $159.7 billion, up 144.3% year on year, with sales through August exceeding $1 trillion. The monthly series is a three-month moving average , not a raw single-month shipment total.

Different forecast vintages also need to remain separate. WSTS’s Spring 2026 outlook projects a $1.51 trillion market for the full year. SIA’s later October statement points to sales above $1.6 trillion. Neither is a completed 2026 result.

These differences matter for a node-focused investment thesis. Memory, logic and analog are separate product markets. Higher industry revenue does not establish how much came from extra production, changes in selling prices or a richer product mix. Nor does it show that every manufacturer has equal pricing power.

Why the AI boom still needs mature processes

SIA and Deloitte’s Powering AI report, published in June 2026, provides a useful system-level check. Its representative AI rack contains roughly 20,000 semiconductor dies packaged into more than 4,500 chips. These are different units: a packaged chip may contain several dies.

The study estimates that semiconductors account for roughly 95% of the rack’s content value. Yet 52% of its chips fall below $10 each, while only 3% sit above $1,000. The report also places most advanced-node dies in the compute tray; other trays depend heavily on more mature technologies.

These figures describe the report’s representative configuration, not every AI rack or the global node mix. Their analytical implication is that value concentration and operational importance are different: an inexpensive supporting component can still prevent an expensive system from operating.

There are clear commercial reasons to preserve multiple process generations. GlobalFoundries continues to develop its 22FDX platform for power-sensitive applications. Texas Instruments highlights 28–130 nm processes optimized for analog and embedded products. A suitable process must deliver the required electrical behaviour and economics; a smaller label alone does not establish suitability.

Capacity is another measure entirely

SEMI’s June 2025 public outlook projected capacity at 7 nm and below rising from approximately 850,000 to 1.4 million 300 mm wafers per month between 2024 and 2028. That gives a useful view of the planned physical expansion, but it is an older forecast, not a measurement of today’s installed or utilized capacity.

Capacity is not production, and wafers are not packaged chips. Utilization (how much capacity is used), die area and yield (the share of usable output) all affect the number of working devices delivered. This is why the capacity chart and TSMC’s revenue chart should be read separately.

What to watch as the next nodes scale

For foundries, watch commercial execution. A technology announcement is a starting point. Evidence of customer adoption, production scale and attractive economics determines how much the node contributes to the business. TSMC’s emerging 2 nm revenue share provides one observable measure; equivalent disclosures are not consistently available across competitors.

For equipment suppliers, watch the manufacturing changes. ASML’s extreme ultraviolet (EUV) lithography systems, which use light to pattern circuits, are relevant to advanced-node manufacturing. But a node label alone does not specify the complete equipment bill or the timing of orders. The investment question is how customers translate their process and capacity plans into spending, then sustain utilization.

For chip designers, watch system economics. More capable logic can lose much of its practical advantage if memory, communication or power delivery constrains the system. Conversely, effective integration can make a product built on an established node highly competitive.

For suppliers of supporting chips, watch content and pricing separately. Being essential to AI infrastructure does not automatically imply high margins. The relevant questions are how many devices a system requires, whether customers can substitute them, and how much capacity is available.

The advance towards 1 nm will remain a defining engineering story. The investable opportunity is distributed more widely: across the new processes, the established nodes that remain economical, and the technologies that connect them into useful systems. The smallest number is a starting point for analysis, not its conclusion.